Introduction
The CA DREAMS and MMEC Hubs of the Microelectronics Commons (MEC) program in conjunction with the Northrop Grumman Microelectronics Center (NGMC) are executing a GaN Design Challenge. This cross-hub collaboration will utilize the MOSIS 2.0 Multi Project Wafer (MPW) fabrication services, the Cross Hub Enablement Solution (CHES) EDA tool access, and the NGMC GaN15 process technology node.
The Problem
The Commons GaN Design Challenge is offering a 5 mm x 5 mm die area on a NGMC GaN15 MPW. The design goal is open in that the designer or design team can define the application and target performance specifications, the technical merit of which will be the primary selection criteria for the challenge. Designers will be expected to clearly describe the target application, circuit design concept, and how proposed design concept will provide novel or unique solutions enabled by advanced GaN technology offering and/or innovative design approach. In addition, individuals or teams are expected to discuss relevant design capability referencing prior circuit design experience, familiarity
Objective
The objective of the Commons GaN Design Challenge is to lower barriers to entry to advanced GaN technology, engage with traditional and non-traditional GaN power amplifier (PA) designers, foster domestic design and fabrication capability, and enable rigorous RF design practices.